Benchmark circuits for clock scheduling and synthesis

Listed in Datasets

By Rickard F. Ewetz1, Shankarshana Janarthanan2, Cheng-Kok Koh1, Chuan Yean Tan1

1. Purdue University 2. NVIDIA corporation

This repository contains experimental data related to our ASP-DAC 2015, ISPD 2015, and DAC2015 publications.

Version 3.0 - published on 31 Mar 2017 doi:10.4231/R7M32SSV - cite this Archived on 02 May 2017

Licensed under CC0 1.0 Universal



This repository contains:

1. The benchmarks circuits used in:

[1] R. Ewetz, S. Janarthanan, C.-K. Koh. Fast clock skew scheduling based on sparse-graph algorithms. ASP-DAC'15, 2015.
[2] R. Ewetz, C.-K. Koh. A Useful Skew Tree Framework for Inserting Large Safety Margins. ISPD'15, 2015.  
[3] C. Sze. ISPD 2010 high performance clock network synthesis contest: Benchmark suite and results. ISPD’10, pages 143–143, 2010.
[4] J. G. Xi and W. W.-M. Dai. Useful-skew clock routing with gate sizing for low power design. DAC ’96, pages 383–388, 1996.
[5] OpenCores.
[6] R. Ewetz, S. Janarthanan, C.-K. Koh. Construction of Reconfigurable Clock Trees for MCMM designs. DAC'15, 2015.
[7] R. Ewetz, C.-K Koh, Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Reduction, TODAES, 2016.
[8]  R. Ewetz and C.-K. Koh. MCMM clock tree optimization based on slack redistribution using a reduced slack graph. ASP-DAC'16, pages 366-371, 2016.
[9]  R. Ewetz, C. Tan, and C.-K. Koh. Construction of latency-bounded clock trees. ISPD '16, 2016.
[10] R. Ewetz and C.-K. Koh. Clock Tree Construction based on Arrival Time Constraints. ISPD'17, 2017.
[11] R. Ewetz, A Clock Tree Optimization Framework with Predictable timing Quality, DAC'17, 2017.



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Updated with additional circuits.

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