This repository contains:
1. The benchmarks circuits used in:
 R. Ewetz, S. Janarthanan, C.-K. Koh. Fast clock skew scheduling based on sparse-graph algorithms. ASP-DAC'15, 2015.
 R. Ewetz, C.-K. Koh. A Useful Skew Tree Framework for Inserting Large Safety Margins. ISPD'15, 2015.
 C. Sze. ISPD 2010 high performance clock network synthesis contest: Benchmark suite and results. ISPD’10, pages 143–143, 2010.
 J. G. Xi and W. W.-M. Dai. Useful-skew clock routing with gate sizing for low power design. DAC ’96, pages 383–388, 1996.
 OpenCores. http://opencores.net/.
 R. Ewetz, S. Janarthanan, C.-K. Koh. Construction of Reconfigurable Clock Trees for MCMM designs. DAC'15, 2015.
 R. Ewetz, C.-K Koh, Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Reduction, TODAES, 2016.
 R. Ewetz and C.-K. Koh. MCMM clock tree optimization based on slack redistribution using a reduced slack graph. ASP-DAC'16, pages 366-371, 2016.
 R. Ewetz, C. Tan, and C.-K. Koh. Construction of latency-bounded clock trees. ISPD '16, 2016.
 R. Ewetz and C.-K. Koh. Clock Tree Construction based on Arrival Time Constraints. ISPD'17, 2017.
 R. Ewetz, A Clock Tree Optimization Framework with Predictable timing Quality, DAC'17, 2017.
Cite this work
Researchers should cite this work as follows:
- Rickard F. Ewetz, Shankarshana Janarthanan, Cheng-Kok Koh, Tan, C. Y. (2017). Benchmark circuits for clock scheduling and synthesis. (Version 3.0). Purdue University Research Repository. doi:10.4231/R7M32SSV
Updated with additional circuits.